Reduced Gate Charge Trench Field-Effect Transistor

ABSTRACT

In one implementation, a trench field-effect transistor (trench FET) can include a semiconductor substrate including a drain region, a drift zone over the drain region, and first and second gate trenches including a gate dielectric and respective gate electrodes disposed therein, also over the drain region. The trench FET can further include a depletion trench situated between the first and second gate trenches, the depletion trench including a trench insulator. The trench insulator adjoins the gate electrodes and the gate dielectric so as to reduce a gate charge of the trench FET.

The present application claims the benefit of and priority to aprovisional application entitled “Reduced Gate Charge Trench MOSFET,”Ser. No. 61/737,038 filed on Dec. 13, 2012. The disclosure in thisprovisional application is hereby incorporated fully by reference intothe present application.

BACKGROUND Background Art

Group IV power transistors, such as silicon based trench typefield-effect transistors (trench FETs) are used in a variety ofapplications. For example, silicon based trenchmetal-oxide-semiconductor FETs (trench MOSFETs) may be used to implementa power converter, such as a synchronous rectifier, or a direct current(DC) to DC power converter.

For many trench FET applications, it is desirable to reduce theon-resistance (R_(dson)) of the transistor. In addition, in applicationsfor which high switching speeds are necessary or desirable, it may alsobe advantageous to reduce gate charge (Q_(g)), so as to reduce switchingloss. However, conventional strategies for reducing on-resistance, suchas increasing channel density for example, typically not only increasegate charge, but may undesirably increase the product of on-resistanceand gate charge (i.e., R_(dson)*Q_(g)) as well.

SUMMARY

The present disclosure is directed to a reduced gate charge trenchfield-effect transistor, substantially as shown in and/or described inconnection with at least one of the figures, and as set forth morecompletely in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a flowchart presenting one exemplary method for fabricatinga reduced gate charge trench field-effect transistor (trench FET).

FIG. 2A shows an exemplary structure corresponding to an initial stageof the method described in FIG. 1.

FIG. 2B shows the exemplary structure in FIG. 2A at an intermediatestage of the method described in FIG. 1.

FIG. 2C shows the exemplary structure in FIG. 2B at another intermediatestage of the method described in FIG. 1.

FIG. 2D shows the exemplary structure in FIG. 2C at another intermediatestage of the method described in FIG. 1.

FIG. 2E shows the exemplary structure in FIG. 2D at another intermediatestage of the method described in FIG. 1.

FIG. 2F shows a cross-sectional view of a reduced gate charge trenchFET, according to one implementation.

FIG. 3 shows a cross-sectional view of a reduced gate charge trench FET,according to another implementation.

DETAILED DESCRIPTION

The following description contains specific information pertaining toimplementations in the present disclosure. One skilled in the art willrecognize that the present disclosure may be implemented in a mannerdifferent from that specifically discussed herein. The drawings in thepresent application and their accompanying detailed description aredirected to merely exemplary implementations. Unless noted otherwise,like or corresponding elements among the figures may be indicated bylike or corresponding reference numerals. Moreover, the drawings andillustrations in the present application are generally not to scale, andare not intended to correspond to actual relative dimensions.

As stated above, group IV power transistors, such as silicon basedtrench type field-effect transistors (trench FETs) are used in a varietyof applications. For example, silicon based trenchmetal-oxide-semiconductor FETs (trench MOSFETs) may be used to implementa power converter, such as a synchronous rectifier, or a direct current(DC) to DC power converter. For many trench FET applications, it isdesirable to reduce the on-resistance (R_(dson)) of the transistor.Moreover, in applications for which high switching speeds are necessaryor desirable, it may also be advantageous to reduce gate charge (Q_(g)),so as to reduce switching loss. However, conventional strategies forreducing on-resistance, such as increasing channel density for example,typically not only increase gate charge, but may undesirably increasethe product of on-resistance and gate charge (i.e., R_(dson)*Q_(g)) aswell.

The present application discloses a group IV trench FET and a method forits fabrication that reduces Q_(g), and in some implementationsconcurrently reduces the product R_(dson)*Q_(g). For example, byconfiguring a gate electrode and a gate dielectric so as to be adjoinedby a thicker trench insulator used to line a depletion trench of thetrench FET, the capacitance between the gate electrode and the siliconor other group IV layer in which a gate trench including the gateelectrode is disposed, can be reduced. As a result, Q_(g) for the trenchFET is reduced, enhancing performance for virtually all high frequencyswitching applications. In addition, for some applications, for examplethose requiring a FET operating voltage of approximately eighty volts(80 V) to approximately 100 V, or higher, the implementations disclosedin the present application can advantageously result in a reduction inthe product R_(dson)*Q_(g).

Referring to FIG. 1, FIG. 1 shows flowchart 100 presenting an exemplarymethod for fabricating a reduced gate charge trench FET, according toone implementation. It is noted that the method described by flowchart100 is performed on a portion of a processed semiconductor wafer or die,which may include, among other features, a silicon substrate and anepitaxially grown silicon layer, for example.

With respect to FIGS. 2A through 2F, structures 210 through 260 shownrespectively in those figures illustrate the result of performing themethod of flowchart 100 on a semiconductor structure, such as a portionof a semiconductor substrate. For example, structure 210 shows a portionof the semiconductor substrate including a drain region and a drift zoneover the drain region (110), structure 220 shows structure 210 afterformation of broad trenches lined by a thin gate dielectric and havingrespective conductive bodies disposed therein (120), structure 230 showsstructure 220 after formation of depletion trenches through theconductive bodies and broad trenches (130), and so forth. It is notedthat although FIGS. 2A through 2F depict fabrication of an n-channelfield-effect transistor (NFET) in silicon, that representation is merelyexemplary. In other implementations, other group IV semiconductors canbe utilized, such as strained or unstrained germanium, for example.Moreover, in some implementations, the present concepts can be adaptedto fabricate a p-channel FET (PFET).

Referring to structure 210, in FIG. 2A, in combination with flowchart100, in FIG. 1, flowchart 100 begins with providing semiconductorsubstrate 212 including drain region 214, and drift zone 216 over drainregion 214 (110). According to the exemplary implementation of FIG. 2A,drain region 214 is shown as an N+ drain region, and drift zone 216 isshown as an N− drift zone situated over drain region 214. Semiconductorsubstrate 212 may be a silicon substrate, for example, and may includedrift zone 216 formed as an epitaxial silicon layer disposed over drainregion 214. Formation of an epitaxial silicon layer may be performed byany suitable method, as known in the art, such as chemical vapordeposition (CVD) or molecular beam epitaxy (MBE), for example.

More generally, however, drift zone 216 may be formed as any suitablegroup IV layer included in semiconductor structure 210. Thus, in otherimplementations, drift zone 216 need not be formed of silicon. Forexample, in one alternative implementation, drift zone 216 can be formedin either a strained or unstained germanium layer formed over drainregion 214 of semiconductor substrate 212. Moreover, in someimplementations, structure 210 may include additional layers, such as abuffer or field stop layer having the same conductivity type as drainregion 214 and drift zone 216, and situated between drain region 214 anddrift zone 216 (buffer or field stop layer not shown in FIG. 2A).

Continuing to refer to flowchart 100, in FIG. 1, with additionalreference to structure 220, in FIG. 2B, flowchart 100 continues withforming broad trenches 222 lined by thin gate dielectric 224 and havingrespective conductive bodies 226 formed therein, over drain region 214(120). Formation of broad trenches 222 can be performed using anytechniques known in the art. For example, in one implementation, aphotoresist layer may be deposited over drift zone 216 and may belithographically patterned to provide a mask for formation of broadtrenches 222 (photoresist layer not shown). Thereafter, a suitable etchprocess may be utilized to form broad trenches 222. An example of asuitable etch process for formation of broad trenches 222 is a dry etchprocess, such as a plasma etch.

Thin gate dielectric 224 may be formed using any material and anytechnique typically employed in the art. For example, thin gatedielectric 224 may be a gate oxide, such as silicon oxide (SiO₂), or agate nitride, such as silicon nitride (Si₃N₄), and may be deposited orthermally grown to produce thin gate dielectric 224. In someimplementations, for example, thin gate dielectric 224 may be a SiO₂layer thermally grown to a thickness in a range from approximately 500angstroms (500 Å) to approximately 1000 Å.

Alternatively, thin gate dielectric 224 may be a high dielectricconstant (high-K) dielectric layer suitable for use in a high-K metalgate process. That is to say, for example, thin gate dielectric 224 maybe formed of a metal oxide such as hafnium oxide (HfO₂), zirconium oxide(ZrO₂), or the like. Moreover, thin gate dielectric 224 can be fanned bydepositing a high-K dielectric material, such as HfO₂ or ZrO₂ so as toline broad trenches 222, utilizing a physical vapor deposition (PVD)process, CVD, or other suitable deposition process.

Conductive bodies 226 may be formed using any material typicallyutilized in the art. For example, conductive bodies 226 may be formed ofconductive polysilicon. However, in implementations in which thin gatedielectric 224 is formed as a high-K dielectric, conductive bodies 226may be formed of gate metal. Thus, when implemented as part of an NFET,such as an n-channel MOSFET, conductive bodies 226 may be formed of agate metal suitable for use as an NFET gate. For example, conductivebodies 226 may be formed of tantalum (Ta), tantalum nitride (TaN),titanium nitride (TiN), or other gate metal suitable for utilization inan NFET gate.

Alternatively, when implemented as part of a PFET, such as a p-channelMOSFET, conductive bodies 226 may be formed of a gate metal suitable foruse as a PFET gate. For example, in those implementations, conductivebodies 226 may be formed of molybdenum (Mo), ruthenium (Ru), or tantalumcarbide nitride (TaCN), for example.

Referring now to structure 230, in FIG. 2C, in combination with FIG. 1,flowchart 100 continues with formation of depletion trenches 232 throughconductive bodies 226 and broad trenches 222 to produce gate trenches234 a and 234 b including thin gate dielectric 224 and respective gateelectrodes 226 a and 226 b (130). Formation of depletion trenches 232can be performed using any techniques known in the art. For example, inone implementation, a photoresist layer may be deposited oversemiconductor structure 220, in FIG. 2B, and may be lithographicallypatterned to provide a mask for formation of depletion trenches 232, inFIG. 2C (photoresist layer not shown). Thereafter, a suitable etchprocess, such as a plasma etch, or other dry etch process, may beutilized to form depletion trenches 232.

As shown in FIG. 2C, depletion trenches 232 extend into drift zone 216,and are situated between respective gate trenches 234 a and 234 b. Asfurther shown in FIG. 2C, depletion trenches 232 are significantlydeeper than gate trenches 234 a and 234 b. For example, in someimplementations, depletion trenches 232 may be from approximately oneand a half times deeper to approximately twice as deep as gate trenches234 a and 234 b. Moreover, in some implementations, it may beadvantageous or desirable for depletion trenches 232 to be more thantwice as deep as gate trenches 234 a and 234 b.

According to the implementation shown in FIG. 2C, depletion trenches areformed through substantially the center of broad trenches 222 of FIG.2B. As a result, the disposition of gate trenches 234 a and 234 bincluding respective gate electrodes 226 a and 226 b is substantiallysymmetrical with respect to depletion trenches 232. Moreover, becausedepletion trenches 232 are formed through conductive bodies 226 andthrough thin gate dielectric 224, depletion trenches 232 adjoin gateelectrodes 226 a and 226 b, and thin gate dielectric 224.

Moving to structure 240 in FIG. 2D with ongoing reference to FIG. 1,flowchart 100 continues with lining of depletion trenches 232 with thicktrench insulator 242, thick trench insulator 242 adjoining gateelectrodes 226 a and 226 b, and thin gate dielectric 224 (140). In someimplementations, as shown in FIG. 2D, thick trench insulator 242 may beformed of the same material used to form thin gate dielectric 224.Moreover, in those implementations, thick trench insulator 242 may beformed using the same technique utilized for formation of thin gatedielectric 224.

That is to say, thick trench insulator 242 may be formed as a thermallygrown oxide, such as silicon oxide. However, it is noted that even whenformed of substantially the same dielectric material and formed usingsubstantially the same fabrication technique, thick trench insulator 242is distinguishable from thin gate dielectric 224 by being substantiallythicker than thin gate dielectric 224. As a specific example, thicktrench insulator 242 may be a SiO₂ layer formed to a thickness in arange from approximately 3000 Å to approximately 6000 Å. By way ofcomparison, and as noted above, thin gate dielectric 224 may be anapproximately 500 Å to approximately 1000 Å SiO₂ layer.

Together, thin gate dielectric 224 and thick trench insulator 242provide gate insulation for gate electrodes 226 a and 226 b. Dispositionof gate electrodes 226 a and 226 b adjoining depletion trenches 232, andthe use of thick trench insulator 242 to form a portion of the gateinsulation for gate electrodes 226 a and 226 b, results in a reducedcapacitance between drift zone 216 and gate electrodes 226 a and 226 brelative to conventional designs. Consequently, the gate charge Q_(g) ofa trench FET, such as a trench MOSFET, fabricated based on the method offlowchart 100 can be expected to be reduced, rendering the MOSFETadvantageous for use in high frequency switching applications.

As shown by structure 250 in FIG. 2E, flowchart 100 continues withformation of respective depletion electrodes 252 in depletion trenches232 (150). Depletion electrodes 252 may be formed of the same materialand using the same technique utilized for formation of gate electrodes226 a and 226 b, i.e., the same material and using the same techniqueutilized for formation of conductive bodies 226, in FIG. 2B. That is tosay, depletion electrodes 252 may be formed of any suitable conductor,such as conductive polysilicon, or metal, for example. Althoughdepletion electrodes 252 can be formed of substantially the samematerial and may be fabricated using substantially the same techniqueused to form gate electrodes 226 a and 226 b, as noted above, in someimplementations it may be advantageous or desirable to form depletionelectrodes 252 using a different conductive material than that used toform gate electrodes 226 a and 226 b.

Continuing with the implementation shown by structure 260 in FIG. 2F,flowchart 100 may conclude with formation of channel layer 262, shown asa P type channel layer, channel contacts 264, also P type, and N typesource regions 266, adjacent gate trenches 234 a and 234 b (160).Channel layer 262 and channel contacts 264 may be formed throughimplantation and diffusion of a P type dopant, such as boron (B) intosemiconductor substrate 212 so as to form channel layer 262 and channelcontacts 264 over drift zone 216. Moreover, N type source regions 266may be formed over drift zone 216 through implantation and diffusion ofan N type dopant, such as phosphorus (P) or arsenic (AS), for example.In one exemplary implementation, diffusion of channel layer 262 andchannel contacts 264 may be followed by a contact etch which removes Ntype species implanted in the region occupied by channel contact 252prior to diffusion of the N type source implant. That contact etch maythen be followed by diffusion of the N type source implant to form Ntype source regions 266.

Depletion electrodes 252 can be used to deplete drift zone 216 when thetrench FET implemented using structure 260 is in the blocking state,when depletion electrodes 252 are tied to a low electrical potential,e.g., grounded or at a near ground potential. For example, in oneimplementation, depletion electrodes 252 may be electrically coupled toa source of the trench FET, such as by being coupled to N type sourceregions 266. In that exemplary implementation, depletion trenches 232correspond to deep source trenches, while depletion electrodes 252 maybe characterized as buried source electrodes. It is noted thatelectrical connection of depletion electrodes 252 and N type sourceregions 266 may be implemented using a metal contact layer overlyingstructure 260 (not shown in FIG. 2F), or may occur in the thirddimension with respect to the cross-sectional view shown in FIG. 2F.

Use of depletion electrodes 252 to deplete drift zone 216 can conferseveral advantages. For example, in one implementation, depletiontrenches 232 including depletion electrodes 252 enable structure 260 tosustain a higher breakdown voltage for higher voltage operation.Alternatively, depletion trenches 232 including depletion electrodes 252enable an increased conductivity for drift zone 216 while sustaining adesired breakdown voltage. The latter implementation may be desirablebecause increased conductivity in drift zone 216 is associated with areduced R_(dson).

Turning now to FIG. 3, structure 300 shows a cross-sectional view of anexemplary reduced gate charge trench FET according to anotherimplementation. Structure 300 includes semiconductor substrate 312including drain region 314, drift zone 316, channel layer 362, andchannel contact 364. As shown in FIG. 3, structure 300 also includesdepletion trenches 332 and 336 extending through channel layer 362 intodrift zone 316. Depletion trenches 332 and 336 each includes thicktrench insulator 342 and depletion electrode 352 disposed therein. Inaddition, depletion trenches 332, but not depletion trench 336, havethin gate dielectric 324 and gate electrodes 326 a and 326 b adjoiningthick trench insulator 342. Also shown in FIG. 3 are gate trenches 334 aand 334 b, and N type source regions 366.

Gate trenches 334 a and 334 b, and depletion trenches 332 includingrespective depletion electrodes 352 and thick trench insulator 342correspond respectively to gate trenches 234 a and 234 b, and depletiontrenches 232 including respective depletion electrodes 252 and thicktrench insulator 242, in FIG. 2F. In addition, thin gate dielectric 324and gate electrodes 326 a and 326 b adjoining thick trench insulator342, in FIG. 3, correspond respectively to thin gate dielectric 224 andgate electrodes 226 a and 226 b adjoining thick trench insulator 242, inFIG. 2. Moreover, semiconductor substrate 312, drain region 314, driftzone 316, channel layer 362, channel contact 364, and N type sourceregions 366, in FIG. 3, correspond respectively to semiconductorsubstrate 212, drain region 214, drift zone 216, channel layer 262,channel contacts 264, and N type source regions 266, in FIG. 2F.

Structure 300, in FIG. 3, differs from structure 260, in FIG. 2F, inthat depletion trench 336 is situated adjacent gate trenches 326 a and326 b adjoining depletion trenches 332. In other words, depletion trench336 is formed between depletion trenches 332 and is not adjoined by gatetrenches 326 a and 326 b. As a result, the channel density of structure300 is reduced relative to the channel density of structure 260, in FIG.2F. For example, where a unit cell of structures 260 or 300 is definedas being bordered by successive depletion trenches, structure 300 can beseen to have approximately one half the channel density of structure260. Consequently, implementation of structure 300 results in a stilllower total gate charge Q_(g) compared to structure 260.

It is noted that, despite the reduction in channel density associatedwith structure 300, for certain higher voltage applications, for exampleapproximately 80 V to approximately 100 V operation, or higher, thereduction in channel density of structure 300 may produce only a nominalincrease in R_(dson). Consequently, for some applications, a trenchMOSFET implementing structure 300 may achieve a reduced gate chargeQ_(g), while concurrently achieving reduction in the productR_(dson)*Q_(g).

Thus, by configuring a gate electrode and a gate dielectric so as to beadjoined by a thicker trench insulator used to line a depletion trenchof a trench FET, the capacitance between the gate electrode and thesilicon or other group IV layer in which a gate trench including thegate electrode is disposed can be reduced. As a result, the gate chargefor the trench FET is reduced, enhancing performance for virtually allhigh frequency switching applications. In addition, for someapplications, for example those requiring a FET operating voltage ofapproximately eighty volts (80 V) to approximately 100 V, or higher, theimplementations disclosed in the present application can alsoadvantageously result in a reduction in the product R_(dson)*Q_(g).

From the above description it is manifest that various techniques can beused for implementing the concepts described in the present applicationwithout departing from the scope of those concepts. Moreover, while theconcepts have been described with specific reference to certainimplementations, a person of ordinary skill in the art would recognizethat changes can be made in form and detail without departing from thescope of those concepts. As such, the described implementations are tobe considered in all respects as illustrative and not restrictive. Itshould also be understood that the present application is not limited tothe particular implementations described herein, but manyrearrangements, modifications, and substitutions are possible withoutdeparting from the scope of the present disclosure.

1. A trench FET comprising: a semiconductor substrate including a drainregion and a drift zone over said drain region; first and second gatetrenches including a gate dielectric and respective gate electrodesdisposed therein, over said drain region; a depletion trench situatedbetween said first and second gate trenches, said depletion trenchincluding a trench insulator; said trench insulator adjoining said gateelectrodes and said gate dielectric so as to reduce a gate charge ofsaid trench FET.
 2. The trench FET of claim 1, wherein said trenchinsulator is substantially thicker than said gate dielectric.
 3. Thetrench FET of claim 1, wherein said depletion trench has a depletionelectrode disposed therein.
 4. The trench FET of claim 1, wherein saiddepletion trench has a depletion electrode disposed therein, saiddepletion electrode electrically coupled to a source of said trench FET.5. The trench FET of claim 1, wherein said depletion trench is at leastone and a half times deeper than said first and second gate trenches. 6.The trench FET of claim 1, further comprising another depletion trenchsituated adjacent at least one of said first and second gate trenches.7. The trench FET of claim 1, further comprising third and fourth gatetrenches including a gate dielectric and respective gate electrodes,situated adjacent said first and second gate trenches, and anotherdepletion trench situated between said third and fourth gate trenches.8. The trench FET of claim 1, further comprising a channel layerincluding source regions formed over said drift zone.
 9. The trench FETof claim 1, wherein said drift zone comprises an epitaxial siliconlayer.
 10. The trench FET of claim 1, wherein said trench FET is ann-channel FET.
 11. A method for fabricating a trench FET, said methodcomprising: providing a semiconductor substrate including a drainregion, and a drift zone over said drain region; forming a broad trenchlined by a gate dielectric and having a conductive body disposedtherein, over said drain region; forming a depletion trench through saidconductive body and said broad trench to produce first and second gatetrenches including said gate dielectric and respective gate electrodes;lining said depletion trench with a trench insulator; said trenchinsulator adjoining said gate electrodes and said gate dielectric so asto reduce a gate charge of said trench FET.
 12. The method of claim 11,wherein said trench insulator is substantially thicker than said gatedielectric.
 13. The method of claim 11, further comprising forming adepletion electrode in said depletion trench.
 14. The method of claim11, further comprising forming a depletion electrode in said depletiontrench, and electrically coupling said depletion electrode to a sourceof said trench FET.
 15. The method of claim 11, wherein said depletiontrench is at least one and a half times deeper than said first andsecond gate trenches.
 16. The method of claim 11, further comprisingforming another depletion trench adjacent at least one of said first andsecond gate trenches.
 17. The method of claim 11, further comprisingforming third and fourth gate trenches including a gate dielectric andrespective gate electrodes, situated adjacent said first and second gatetrenches, and another depletion trench situated between said third andfourth gate trenches.
 18. The method of claim 11, further comprisingforming a channel layer including source regions over said drift zone.19. The method of claim 11, wherein said drift zone comprises anepitaxial silicon layer.
 20. The method of claim 11, wherein said trenchFET is an n-channel FET.